The present invention relates to a method and business management tool for analyzing, comparing and assessing an electronic design validation process. More particularly, an embodiment of the present invention analyses, compares and assesses electronic design validation process associated with the validation of a design for an integrated circuit such as a microprocessor, ASICS, a chip or chip set.
Today's microprocessor design validation processes are largely simulation-centric, using model-checking to detect a relative few but very difficult corner-case design errors and relying on large simulation compute-farms, whose practicality and effectiveness have been made possible by advances in testbench languages and code coverage technologies, to detect the vast preponderance of specification and design errors. However, error detection is accomplished late in the validation cycle when the full-chip is verified.
Another electronic design validation process, an isomorphism-centric validation process, somewhat reverses the strategy of the simulation-centric validation process. Starting at the functional block level, an isomorphism-centric validation process uses isomorphism-checking, a very robust but indirect method of formal verification, to detect the vast preponderance of design errors made earlier and upstream in the design process. Then it focuses the power of simulation compute-farms on possible specification errors and the few remaining design errors. To date there is no relatively simple and effective technique to assess and compare these two, or any other, disparate electronic design validation process strategies. What is needed is a method and management tool that can be used to analyze, compare, contrast, and assess an electronic design validation process. Furthermore, what is needed is a method and management tool for effectively comparing a plurality of electronic design validation processes with each other.